The present invention relates to a data sense circuit, and more particularly to a data sense circuit for sensing data by using current difference in a semiconductor circuit.
The prior art regarding the data sense circuit will be described with reference to FIG. 1 and FIG. 2. As shown in FIG. 1, the data sense circuit of the prior art was composed of the bit line sense amplifying part 1, switching n channel FET's (N2 and N3) connected to the data bus lines (DL1 and DL2), the capacitors (CDB and CDB1), and the data bus line sense amplifier 2. The bit line sense amplifying part was composed of the n channel FET(NL) which the gate thereof was connected to the word line and the source thereof was connected to the bit line (BL1), the bit line sense amplifier 11 connected to between the bit lines (BL1 and BL2), and the capacitors (CBL and CBL1) Connected to the bit lines (BL1 and BL2), and the data bus line sense amplifier 2 was composed of the p channel MOSFET (Pi) which the drain thereof was connected to the gate thereof, the p channel MOSFET (P2) which the source and the gate thereof were connected to the source and the gate of the p channel MOSFET(Pl), the n channel MOSFET's (N4 and N5) which the drains thereof were connected to the drains of the p channel MOSFET's (P1 and P2) and the gates thereof were connected to the drains of the n channel MOSFET's (N2 and N3), and the n channel MOSFET (N6) which the drain thereof was connected to the source of the n channel MOSFET's (N4 and N5).
If the data word line selection signal TWL(.phi.0) is applied to the n channel MOSFET (N1), the voltage difference between the bit lines is caused by the data stored in the memory cell (not shown in FIG. 1). If the sense amplifier 11 is operated by the operating signal (.phi.1), the voltage difference between the bit lines (BL1 and BL2) is amplified and the switching operating signal (.phi.2) is applied to the switching MOSFET (N2 and N3) so that this amplified voltage is sent to the data bus lines (DL1 and DL2). Then, changing share is caused by the bit line capacitors (CBL and CBL1) and data line capacitors (CDB and CDB1) and as shown in FIG. 2, the voltage offset occurs. And then according to the operating signal (.phi.3), the data bus line sense amplifier 2 is operated and outputs the voltage difference.
The data sense circuit of the prior art had problems that the operating time was delayed and power consumption was caused by said charge share in the capacitors, and that the operating time was delayed more because the voltages of the bit lines and the data bus lines were recharged to the same voltage after data sense operation.